– Perform physical design implementation
Including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.
– The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power design.
– The responsibility includes participating in or leading next generation physical design, methodology and flow development.
– BSEE or equivalent, MS preferred
– 3+ years of experience in VLSI physical design implementation and methodology
– Successful track record of delivering products to production a must
– Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, place and route, DRC/LVS and etc.
– Working knowledge of deep sub-micron routing issues as they relate to power and timing
– Should be a power user of P&R CAD tools from Cadence (EDI), Synopsys (ICC/ICC2), or Mentor Graphics (Olympus)
– Knowledge of Perl, TCL, Make scripting is preferred