招聘

上海富芮坤作为一家以技术为本的创业型芯片设计公司,坚信人才是我们公司最宝贵的资源。我们非常欢迎各位大家加入公司的大家庭,一起创造出美好的未来。

目前公司开放以下岗位,请有意向的朋友将简历投至 hr@freqchip.com ,谢谢。

岗位职责:
1、负责各种常用 IP(UART、I2C、SPI、I2S、USB接口等)的设计;
2、负责时钟复位模块的方案制定、设计、仿真验证;
3、负责SOC相关的集成设计、系统设计、架构设计,及集成、仿真验证。

任职要求:
1、电子、通信、计算机或微电子专业本科及以上学历;
2、熟练掌握Verilog、System Verilog等语言的编程,有扎实的数字电路基础;
3、熟练应用EDA工具进行SoC芯片的模块仿真集成与FPGA验证;
4、在以下相关的模块或接口(其中之一)有一定的工作经验:UART、SPI、I2S、Flash接口、USB接口等;
5、有低功耗SoC芯片设计及无线芯片的研发经验者优先考虑;
6、具有较强的学习、沟通能力和良好的团队合作精神。

岗位职责:
芯片上嵌入式软件的功能实现及调试

任职要求:
1.有责任心和抗压能力,能深入专研疑难问题
2.快速的学习能力
3.熟悉C语言编程

Position Description:
– Perform physical design implementation
Including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.
– The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power design.
– The responsibility includes participating in or leading next generation physical design, methodology and flow development.

Position Requirements:
– BSEE or equivalent, MS preferred
– 3+ years of experience in VLSI physical design implementation and methodology
– Successful track record of delivering products to production a must
– Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, place and route, DRC/LVS and etc.
– Working knowledge of deep sub-micron routing issues as they relate to power and timing
– Should be a power user of P&R CAD tools from Cadence (EDI), Synopsys (ICC/ICC2), or Mentor Graphics (Olympus)
– Knowledge of Perl, TCL, Make scripting is preferred